MLIR n-D vector products are presently portrayed while the (n-1)-D arrays of just one-D vectors whenever reduced so you’re able to LLVM

The fresh new implication of the bodily HW limitations on coding design try this one cannot index dynamically around the gear records: a register document can fundamentally never be detailed dynamically. The reason being the brand new sign in amount is fixed and another often has to unroll clearly to find fixed register quantity or wade thanks to recollections. This can be a constraint common in order to CUDA coders: whenever declaring a private float a good ; and you will next indexing with an energetic value contributes to very-entitled regional memories utilize (we.e. roundtripping to thoughts).

Implication into codegen ¶

That it brings up the results on static versus vibrant indexing chatted about previously: extractelement , insertelement and you may shufflevector on the letter-D vectors in the MLIR just service fixed indicator. Vibrant indicator are only served with the extremely lesser step one-D vector yet not this new outside (n-1)-D . Some other circumstances, specific weight / stores are required.

1. Loops doing vector thinking was indirect handling away from vector viewpoints, they need to run on direct weight / shop functions over n-D vector systems.
2. Shortly after an enthusiastic letter-D vector types of try piled towards an enthusiastic SSA value (that or might not reside in letter registers, having otherwise in place of spilling, when sooner or later paid off), it may be unrolled so you can smaller k-D vector types and processes one to match the fresh HW. So it amount of MLIR codegen escort service San Angelo resembles check in allowance and spilling you to definitely occur far later from the LLVM pipeline.
3. HW could possibly get service >1-D vectors having intrinsics getting secondary approaching within these vectors. These could getting targeted by way of direct vector_cast surgery away from MLIR k-D vector versions and processes to LLVM step one-D vectors + intrinsics.

As an alternative, we argue that physically decreasing so you’re able to an effective linearized abstraction hides out this new codegen intricacies linked to recollections accesses by giving an untrue impression of magical active indexing round the information. Instead we always generate those people most specific into the MLIR and you may create codegen to explore tradeoffs. More HW requires some other tradeoffs on the products working in measures 1., dos. and you will 3.

Decisions generated during the MLIR top will receive ramifications at the a beneficial far later stage in the LLVM (immediately following register allotment). We do not envision to expose concerns pertaining to modeling regarding register allotment and you may spilling in order to MLIR explicitly. Rather, for every address usually present a collection of “good” address procedures and letter-D vector versions, for the costs one to PatterRewriters at MLIR level will be able to target. Like will cost you at the MLIR level will be conceptual and you may made use of having ranking, not getting perfect show modeling. In the future particularly will set you back could well be discovered.

Implication for the Lowering to Accelerators ¶

To target accelerators that support higher dimensional vectors natively, we can start from either 1-D or n-D vectors in MLIR and use vector.cast to flatten the most minor dimensions to 1-D vector where K is an appropriate constant. Then, the existing lowering to LLVM-IR immediately applies, with extensions for accelerator-specific intrinsics.

It is the role of an Accelerator-specific vector dialect (see codegen flow in the figure above) to lower the vector.cast . Accelerator -> LLVM lowering would then consist of a bunch of Accelerator -> Accelerator rewrites to perform the casts composed with Accelerator -> LLVM conversions + intrinsics that operate on 1-D vector .

Some of those rewrites may need extra handling, especially if a reduction is involved. For example, vector.cast %0: vector to vector when K != K1 * … * Kn and some arbitrary irregular vector.cast %0: vector<4x4x17xf32> to vector may introduce masking and intra-vector shuffling that may not be worthwhile or even feasible, i.e. infinite cost.

However vector.cast %0: vector to vector when K = K1 * … * Kn should be close to a noop.